1. Field of the Invention
The present invention relates generally to the design of integrated circuits. More specifically, but without limitation thereto, the present invention relates to methods of representing an integrated circuit design for simulating the operation of the integrated circuit.
2. Description of Related Art
Previous methods of simulating application specific integrated circuit (ASIC) functions are based on logical schematic netlists and RC (resistance and capacitance) extraction. Accurate simulation and analysis of large structured arrays in sub-micron technologies, such as memories and datapaths, generally require back-annotation of RC parasitics. The RC parasitics are the resistance and capacitance values of the interconnections between components in the integrated circuit that are important to an accurate simulation of the operation of the integrated circuit. Simulations of large structured arrays typically include only capacitance values or RC simulations of selected portions of specific nets in a large structured array.